In a 1T (Transistor)-1C (Capacitor) ferroelectric memory, a reference voltage VDC needs to be set to an intermediate potential between data “0” and data “1” for a sense amplifier to detect digital data. It is known that a potential of a bit line that transfers the data “0” and the data “1” depends on both a temperature and an array voltage VAA. Accordingly, the intermediate potential between the data “0” and the data “1” also changes with changes of the temperature and the array voltage VAA. The array voltage VAA is applied to a bit line and a plate line at the time of reading or writing data.
However, conventionally, the reference voltage VDC has not depended on both the temperature and the array voltage VAA. Particularly, in recent years, a sense margin of data has become stringent due to downscaling of a memory cell. Furthermore, an external power source voltage VDD has been lowered with the downscaling of the memory cell, and therefore, it is being considered to use the external power source voltage VDD as it is as the array voltage VAA. The external power source voltage VDD varies in a certain level of range. Therefore, when the reference voltage VDC is constant, it is highly possible that the reference voltage VDC is shifted from the intermediate potential between the data “0” and the data “1” due to changes of the temperature and the external power source voltage VDD (array voltage VAA), eventually causing the sense amplifier to detect data erroneously.
Besides, a degree of dependence (amount of dependence) of the reference voltage VDC on the temperature and the external power source voltage VDD (array voltage VAA) has never been considered before.